Embedded Decoupling Capacitance
DoD Participants: U.S. Army – Tobyhanna Army Depot
This document presents the findings of the Embedded Decoupling Capacitance Project, conducted by a consortium team of members from industry, education, and government under administrative oversight by the National Center for Manufacturing Sciences (NCMS).
Electronic products are increasing rapidly in component packaging density and speed. These advances are is placing increasing demands on the interconnect structure to provide not only higher wiring capacity, but also better electrical performance. The printed wiring board (PWB) structure itself is becoming increasingly more important in achieving good signal integrity and meeting standards for radiated emissions.
The need for power-ground decoupling capacitance is nearly universal in electronic circuits. Today, this need is satisfied through discrete chip capacitors. However, as circuit designs increase in speed, the effective use of decoupling capacitors is becoming more difficult to achieve. The parasitic inductance associated with the circuit connections of the decoupling capacitors decreases their effectiveness at higher frequencies. Furthermore, few designers or engineers understand, with any rigor, how many decoupling capacitors are required, how much capacitance they should have, and where to locate them on the circuit. Decoupling capacitors also require valuable amounts of PWB surface area, consuming up to 50% of the total board area.
The increasing packaging densities are creating a desire to free up valuable surface real estate currently occupied by discrete capacitors. New capacitive materials, physically and chemically compatible with standard fire retardant grade 4 laminate (FR-4) material, are being developed as one potential solution to this challenge.
Consequently, in 1998, NCMS and Storage Technology Corporation (StorageTek) initiated and organized the Embedded Decoupling Capacitance (EDC) Project, aimed at advancing the technology of embedded components. Specific areas of interest were the use of embedded capacitance to reduce the number of surface-mounted capacitors used for power supply decoupling and electromagnetic compatibility (EMC).
The goal of the EDC Project was to evaluate the performance of distributive embedded capacitance in circuit boards for power supply decoupling and electromagnetic interference (EMI) suppression and to compare the results with standard surface mount technology (SMT). To achieve this goal, it was necessary to demonstrate that available EDC materials are manufacturable, that they have the physical properties to electrically perform as discrete capacitors do, and that PWBs containing them are reliable. It was also important to understand power supply decoupling, and to develop the ability to predict how and when embedded capacitance will work for a given circuit design. The project took some of the first steps towards the realization of embedded passives in organic substrates.
The 30-month EDC Project effort was co-sponsored by the Department of Defense (DoD) Commercial Technologies for Maintenance Activities (CTMA) Program. CTMA is a partnership between the NCMS and the DoD.
The objective of the CTMA program is to bring advanced commercial technologies to bear on the operations and problems of the DoD logistics activities. Under this agreement, NCMS and its member companies co-sponsor technology development, deployment, and validation with the DOD and its organic maintenance activities.
The current focus is the use of manufacturing technologies to reduce the costs associated with maintenance and rebuild of weapons systems as an element of the overall maintenance strategy. By partnering with NCMS members, the organic maintenance activities are able to quickly assess and apply the benefits of new manufacturing technologies in their own facilities while working side-by-side with industry leaders in solving manufacturing problems through collaboration.
The EDC Project was organized to encompass the entire electronics manufacturing chain, from materials suppliers to the original equipment manufacturers (OEMs). During the formation of the project, it was recognized that the most important deliverable would be an improved understanding of decoupling capacitance – especially if that understanding could be presented in formats that would be useful to circuit designers and circuit fabricators. This approach is reflected in the membership of the project and in the project plan.
The initial project organizational meeting drew representatives from some 40 organizations, indicating widespread interest within the North American electronics industry. Ultimately, 17 highly reputable and diverse organizations formed the consortium to conduct the project.
The primary objective was to evaluate embedded capacitance materials in circuit boards for power supply decoupling and EMI suppression and to compare the results with standard SMT design practices. The secondary objective was to develop preliminary design guidelines for use with selected technologies.
Each capacitive material was provided in sheet form with 1-oz copper cladding on each side.
Each material was sent to two or more board fabricators for incorporation into multilayer PWB. Each fabricator also made boards with FR-4 materials to provide points of comparison should problems or unexpected issues arise during fabrication or testing. The resulting boards were sent to Delphi for reliability testing and to the University of Missouri–Rolla for measurements of power bus noise and radiated emissions, and modeling. Additional EMI testing was done at StorageTek. The embedded capacitance materials were also sent to Penn State and NIST for materials characterization.
Separate test vehicles were designed for reliability testing, electrical testing, and high-frequency performance. The reliability test vehicle had structures designed for materials characterization below 10 GHz as well as for reliability testing. The electrical test vehicle was built with several different stack-ups to permit the evaluation of the relative importance of shielding and decoupling. The microstrip test vehicle was developed to determine high-frequency performance above 10 GHz.
The project developed the processes required to embed thin materials into FR-4 to form a high-capacitance layer between power and ground planes. The project measured the physical and electrical properties of the embedded materials, and determined their effectiveness in suppressing noise between power and ground, at frequencies up to the microwave. The project also determined the reliability of planar capacitance.
Using the physical and electrical properties measured, and the noise suppression characteristics, a model was developed that allows engineers to understand, in advance, the effectiveness of embedded capacitance and the need (or lack of need) for discrete chip capacitors. It is anticipated that, in many cases, this understanding, plus the use of embedded capacitance, will result in lower system lifecycle cost. It is also anticipated that, in almost all cases, the noise suppression characteristics of embedded capacitance will be superior to those of discrete capacitors especially at high frequencies.
The Embedded Decoupling Capacitance Project has demonstrated that embedded capacitance technology is an effective alternative to the use of discrete decoupling capacitors for power supply decoupling. Many benefits to design and assembly activities will be realized as this technology evolves.
The major conclusions of the project are as follows.
Materials characterization testing produced very useful data regarding the physical properties of the embedded capacitance materials. The work resulted in determining the performance over a wide temperature and frequency range. A new test method for measuring time domain reflectometer (TDR) response of embedded capacitance materials was developed. The overall results were favorable enough to encourage continued development work by the materials suppliers.
Board fabrication efforts showed that embedded capacitance materials can be used successfully to build PWBs. Only minor modifications to board fabrication processes were required. However, special design considerations must be met.
All the embedded capacitance materials demonstrated equivalent or better reliability performance compared to FR-4 materials. Specifically, plated-through hole integrity was not compromised by the presence of embedded capacitance materials in the test vehicles.
All of the embedded capacitance materials exhibited sufficient loss to dampen power bus resonances. At frequencies above 1 GHz, embedded capacitance continued to dampen power bus resonances while discrete capacitors were shown ineffective. Further, embedded capacitance boards exhibited the same or lower radiated emissions than FR-4 boards with discrete capacitors.
Project data was used to validate electrical models of power bus structures at UMR. A set of preliminary design considerations was developed.